The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing an anti-fuse in which a portion of the anti-fuse is located between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material of an III-V aspect ratio trapping structure. The present application also relates to a method of forming such a semiconductor structure.
III-V compound semiconductor material co-integration is one technology option for future complementary metal oxide semiconductor (CMOS) nodes. III-V compound semiconductor materials typically require an aspect ratio trapping process to reduce defect levels to a reasonable number to manufacture high performance semiconductor devices. Anti-fuses are used in a variety of circuit applications, also in III-V compound semiconductor material containing circuits. An anti-fuse is an electrical device that performs the opposite function to a fuse. Whereas a fuse starts with a low resistance and is designed to permanently break an electrically conductive path (typically when the current through the path exceeds a specified limit), an anti-fuse starts with a high resistance and is designed to permanently create an electrically conductive path (typically when the voltage across the anti-fuse exceeds a certain level). It is highly desirable to fabricate on-chip anti-fuses during CMOS fabrication to minimize process cost and improve system integration.